The present invention relates to a semiconductor integrated circuit formed by mounting, on one chip, a clock synchronous type circuit that operates synchronously with a clock signal and a clock non-synchronous type circuit that operates asynchronously with a clock signal.
Recently, with advances in process technology, a great reduction in the size of semiconductor devices and a great increase in packing density have been achieved. With this achievement, an overall system can be mounted on one chip by mounting a plurality of functional blocks on the chip.
Under the circumstances, a semiconductor integrated circuit has also been implemented, which is formed by mounting, on one chip, a clock synchronous type circuit that operation synchronously with a clock signal and a clock non-synchronous type circuit that operates asynchronously with a clock signal.
In a semiconductor integrated circuit on which both a clock synchronous type circuit and clock non-synchronous type circuit are mounted, since data cannot be directly exchanged between the clock synchronous type circuit and the clock non-synchronous type circuit, a storage circuit (latency control circuit) capable of setting a so-called latency is placed between the two circuits.
In this case, “latency” indicates a latency period between the instant at which data is output from the clock non-synchronous type circuit and the instant at which the data is input to the clock synchronous type circuit, and is generally expressed by the number of clocks (letting one period of a clock signal be one clock).
Data is therefore exchanged between the clock synchronous type circuit and the clock non-synchronous type circuit through the storage circuit.